The present invention relates generally to apparatuses and methods for testing electrical characteristics of IC (Integrated Circuit) devices, and more particularly to an improved IC testing apparatus and method that are capable of analyzing a specific cause of a failure or defect in each IC. It should be obvious that the term "IC" as used herein also refers to an LSI (Large-Scale Integrated circuit).
To ship mass-produced IC devices as final, finished products of guaranteed performance and quality, it is absolutely necessary to inspect electrical characteristics of all or some of the IC devices at individual stages of manufacturing and testing stations.
Various IC testing apparatuses have been widely known, which are designed to test electrical characteristics of ICs. For testing the electrical characteristics, the known IC testing apparatuses, in general, first feed predetermined test patten data to each IC to be tested and then reads out data, output from the IC in response to the fed test patten data, to determine therefrom whether or not the IC has any trouble with its basic behavior and function.
More specifically, in the "function test" performed by the known IC testing apparatuses, predetermined test patten data are first fed from a pattern generating section to the input terminals of each IC to be tested, and data output from the IC in response to the test patten data are then read and examined to determine whether or not the IC has any trouble with its basic behavior and function. Namely, the function test is intended to check output timing, output amplitudes, etc. of the IC, by varying input timing and amplitudes, etc. of various signals and data, such as address, data, write-enable signal and chip-select signal, to be fed to the IC.
Where the IC device to be tested is a memory, the IC testing method typically feeds address data and test pattern data to the IC so that the test pattern data are written in the IC at various addresses designated by the address data. Then, the same address data are again given to the IC to read out the data from the same addresses to check whether or not the read-out data match the test pattern data previously written as "expected value" data. After that, test results, each of which is a one-bit data of logical value "0" or "1" representing a "pass" (i.e., a successful result in the test) or "fail" (i.e., an unsuccessful result in the test), are recorded at individual addresses of a fail bit memory corresponding to an address map of the IC. In this way, test result data of logical values "0" and "1" representing a "pass" and "fail" are mapped to the corresponding addresses in the fail bit memory corresponding to the IC's address map.
The "pass/fail" pattern data thus stored in the fail bit memory are utilized for further IC analysis tests depending on an intended purpose. Normally, such IC analysis tests typically include a curability determining analysis test and defect analysis test.
In an attempt to correct or cure failed or defective bits of the IC, the curability determining analysis test is designed to map the failed-bit area of the IC to an address space of the fail bit memory during the course of the actual test of the IC's electric characteristics. Immediately after the mapping, the stored data are read out from the fail bit memory in order to substitutively allocate addresses, associated with the failed bits, to redundant lines in the IC. Specifically, this curability determining analysis test is conducted, on the IC mass production line or process, to determine whether the tested IC is "indefective" or "defective" and whether the IC, if determined as defective, is curable or not, and then actually cures the failed bits on the basis of the determination results.
Note that the term "cure" as used herein refers to rearranging the address input logic of the IC in such a manner that a physical space of given addresses having determined as "defective" or "failed" is replaced by an extra (redundant) physical space and thereby placing all the defective addresses of the IC in a usable condition. If the number of failed or defective addresses is smaller than the number of usable addresses in the extra (redundant) physical space, then the IC in question will be determined as "curable", but if the number of failed or defective addresses is greater than the number of usable addresses in the extra physical space, the IC will be determined as "incurable". The above-mentioned curability determining analysis test operates to not allocate the usable addresses to the IC's defective area while allowing the usable addresses to be allocated only to its indefective area; thus each IC with some defective area can be cured into an acceptable IC and an enhanced yield of ICs is achieved. Therefore, it is desired that such a curability determining analysis test be carried out with top priority on the IC mass production line. Generally, the curability determining analysis test is performed on the IC mass production line for every manufactured IC.
On the other hand, the defect analysis test is designed to analyzing a specific cause of a failure or defect in the IC as well as mapping a failed-bit area to an address space in the fail bit memory. For these purposes, the defect analysis test uses the stored contents of the fail bit memory but also various test parameters such as address data and test pattern data used in the pass/fail test and would take a considerable amount of time. Through this defect analysis test, it is possible to ascertain details of a defect, such as whether the defect is present at a particular tiny spot or a relatively extensive area on the surface of the IC or in the shape of a horizontal or vertical narrow line. Thus, the defect analysis test can be useful for identification of a specific cause of a detected failure or defect, quality control and management of various production stages.
In some cases, such defect analysis test is performed off the mass production line extractively for selected ones of the manufactured ICs rather than on the mass production line for every manufactured IC, but such an extractive defect analysis test is not desirable from a viewpoint of quality control. Namely, from the viewpoint of quality control, it is preferred to perform the defect analysis test for every manufactured IC, which would, however, present the problem that a longer test time is required. However, because the curability determining analysis test and defect analysis test are performed separately, execution of the two tests would result in each test cycle taking a longer time, thus leading to low IC-mass production efficiency. In addition, because the curability determining analysis test and defect analysis test are carried out using completely separate testing apparatuses, the conventional approach would require relatively high costs.
In particular, for satisfactory defect analysis, it is necessary to analyze an entire semiconductor wafer from which the IC chip in question is produced, rather than that IC chip alone; to this end, in the defect analysis test, it is necessary to accumulate fail data on every IC chip produced from a same IC chip. For example, in a situation where hundreds of IC chips are formed on a single semiconductor wafer, data to be accumulated for this purpose would amount to a huge quantity; in this case, acquiring the huge quantity of data alone would take an enormous amount of time and subsequently analyzing the acquired data would take an additional enormous amount of time. As a result, the poor efficiency of the conventional approach would present an even more serious problem.